The present invention relates to a charge pump circuit which charges up a voltage supplied from an external device (e.g., a power source) and produces a charged-up voltage.
FIG. 19 shows an arrangement of a conventional charge pump circuit.
A power source 1 is connected via a diode 2 to a positive terminal of a first capacitor 3. A connecting point between the diode 2 and the positive terminal of the capacitor 3 is connected via a diode 4 to a positive terminal of a second capacitor 5. A negative terminal of the capacitor 3 is connected to an output terminal of an oscillator 7 via an inverter 8. A negative terminal of the capacitor 5 is connected to the output terminal of the oscillator 7 via serial inverters 9 and 10. The oscillator 7 produces an oscillation signal (i.e., clock signal) having a constant frequency. An output terminal 6, connected to a connecting point between the diode 4 and the positive terminal of the capacitor 5, produces a charged-up voltage. The inverters 8 to 10 have CMOS circuit arrangements.
According to the above-described conventional circuit arrangement, when the oscillator 7 produces a high-level output signal, the inverter 8 generates a low-level output signal. Therefore, the capacitor 3 is charged up to a power source voltage level through its positive terminal connected via the diode 2 to the power source 1.
When the oscillator 7 produces a low-level output signal, the inverter 8 generates a high-level output signal. Therefore, the negative terminal of the capacitor 3 has an electrical potential equal to the power source voltage. The positive terminal of the capacitor 3 is charged up to a predetermined voltage which is equivalent to two times the power source voltage minus a voltage drop V.sub.F at the diode 2.
Furthermore, when the oscillator 7 produces a low-level output signal, the inverter 10 generates a low-level output signal. The positive terminal of the capacitor 5 may have an electric potential lower than a predetermined value which is equivalent to the electric potential of the positive terminal of the capacitor 3 minus the voltage drop V.sub.F at the diode 4. In this case, electric charges can flow from the positive terminal of the capacitor 3 to the positive terminal of the capacitor 5 by the rectifying function of the diode 4. Thus, the positive terminal of the capacitor 5 is charged up to a predetermined voltage which is equivalent to two times the power source voltage minus a voltage drop 2.times.V.sub.F at the diodes 2 and 4.
Next, when the oscillator 7 produces a high-level output signal, the inverter 10 generates a high-level output signal. The negative terminal of the capacitor 5 has an electrical potential equal to the power source voltage. The positive terminal of the capacitor 5 is charged up to a predetermined voltage which is equivalent to three times the power source voltage minus the voltage drop 2.times.V.sub.F at the diodes 2 and 4. The charged-up voltage is supplied via the output terminal 6 to an electric load connected to this output terminal 6.
However, the above-described conventional circuit arrangement is disadvantageous in that a stable and desirable charged-up voltage is not obtained because the oscillator 7 is provided as an external component. For example, when the oscillator 7 has a higher oscillation frequency, the capacitors 3 and 5 cannot follow the charging and discharging operations. The charged-up voltage cannot reach a desired voltage value. Even when the oscillator 7 has a constant oscillation frequency, dispersions in the capacity and charge/discharge currents of capacitors 3 and 5 as well as their temperature dependencies possibly vary the electrical potentials of the positive terminals of capacitors 3 and 5. Thus, the charged-up voltage will be varied undesirably.